1. Technical Field of the Invention
The present invention relates to the field of integrated circuit, and more particularly to three-dimensional memory (3D-M).
2. Prior Arts
Three-dimensional memory (3D-M) is a monolithic semiconductor memory comprising a plurality of vertically stacked memory cells. It includes three-dimensional read-only memory (3D-ROM) and three-dimensional random-access memory (3D-RAM). The 3D-ROM can be further categorized into three-dimensional mask-programmed read-only memory (3D-MPROM) and three-dimensional electrically-programmable read-only memory (3D-EPROM). 3D-M may further comprise at least one of a 3D-memristor, 3D-RRAM or 3D-ReRAM (resistive random-access memory), 3D-PCM (phase-change memory), 3D-PMC (programmable metallization-cell memory), and 3D-CBRAM (conductive-bridging random-access memory).
U.S. Pat. No. 5,835,396 issued to Zhang on Nov. 3, 1998 discloses a 3D-M, more particularly a 3D-ROM. As illustrated in FIG. 1A, a 3D-M die 20 comprises a substrate-circuit level 0K and a plurality of vertically stacked memory levels 16A, 16B. The substrate-circuit level 0K comprises substrate transistors 0t and substrate interconnects 0i. The substrate transistors 0t are formed in a semiconductor substrate 0. The substrate interconnects 0i are the interconnects for the substrate transistor 0t. In this example, the substrate interconnects 0i includes metal layers 0M1, 0M2. Hereinafter, the metal layers 0M1, 0M2 in the substrate interconnects 0i are referred to as substrate interconnect layers; the materials used in the substrate interconnects 0i are referred to as substrate interconnect materials.
The memory levels 16A, 16B are stacked above the substrate-circuit level 0K. They are coupled to the substrate 0 through contact vias (e.g., 1av). Each of the memory levels (e.g., 16A) comprises a plurality of upper address lines (e.g., 2a), lower address lines (e.g., 1a) and memory cells (e.g., 5aa). The memory cells could comprise diodes, transistors or other devices. Among all types of memory cells, the diode-based memory cells are of particular interest because they have the smallest size of ˜4F2, where F is the minimum feature size. Since they are generally located at the cross points between the upper and lower address lines, the diode-based memory cells form a cross-point array. Hereinafter, diode is broadly interpreted as any two-terminal device whose resistance at the read voltage is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage. In one exemplary embodiment, diode is a semiconductor diode, e.g., p-i-n silicon diode. In another exemplary embodiment, diode is a metal-oxide diode, e.g., titanium-oxide diode, nickel-oxide diode.
The memory levels 16A, 16B form at least a 3D-M array 16, while the substrate-circuit level 0K comprises the peripheral circuit for the 3D-M array 16. A first portion of the peripheral circuit is located underneath the 3D-M array 16 and it is referred to as under-array peripheral circuit. A second portion of the peripheral circuit is located outside the 3D-M array 16 and it is referred to as outside-array peripheral circuits 18. Because the outside-array peripheral circuit 18 comprises significantly fewer back-end-of-line (BEOL) layers than the 3D-M array 16, the space 17 above the outside-array peripheral circuits 18 is empty and completely wasted. Hereinafter, a BEOL layer refers to the layer(s) defined by a single photolithography step during BEOL processing. In FIG. 1A, the 3D-M array 16 comprises fourteen BEOL layers, including two for each interconnect layer (e.g., 0M1, 0M2) and five for each memory level (e.g., 16A, 16B). On the other hand, the outside-array peripheral circuit 18 comprises only four BEOL layers, including two for each substrate interconnect layer (e.g., 0M1, 0M2).
U.S. Pat. No. 7,383,476 issued to Crowley et al. on Jun. 3, 2008 discloses an integrated 3D-M die, whose 3D-arrays and peripheral circuit are integrated on a same die. As is illustrated in FIG. 1B, an integrated 3D-M die 20 comprises a 3D-array region 22 and a peripheral-circuit region 28. The 3D-array region 22 comprises a plurality of 3D-M arrays (e.g., 22aa, 22ay) and their decoders (e.g., 24, 24G). These decoders include local decoders 24 and global decoders 24G. The local decoder 24 decodes address/data for a single 3D-M array, while the global decoder 24G decodes global address/data 25 to each 3D-M array.
The peripheral-circuit region 28 comprises all necessary peripheral-circuit components for a standalone integrated 3D-M die 20 to perform basic memory functions, i.e., it can directly use the voltage supply 23 provided by a user (e.g., a host device), directly read data 27 from the user and directly write data 27 to the user. It includes a read/write-voltage generator (VR/VW-generator) 21 and an address/data translator (A/D-translator) 29. The VR/VW-generator 21 provides read voltage VR and/or write (programming) voltage VW to the 3D-M array(s). The A/D-translator 29 converts address and/or data from a logical space to a physical space and/or vice versa. Hereinafter, the logical space is the space viewed from the perspective of a user of the 3D-M, while the physical space is the space viewed from the perspective of the 3D-M.
The VR/VW-generator 21 includes a band-gap reference generator 21B, a VR generator 21R and a charge-pump circuit 21W. Among them, the band-gap reference generator 21B is a precision reference generator; the VR generator 21R generates the read voltage VR; and, the charge-pump circuit 21W generates the write voltage VW (referring to U.S. Pat. No. 6,486,728, “Multi-Stage Charge-pump circuit”, issued to Kleveland on Nov. 26, 2002). The integrated 3D-M die 20 generates both read voltage and write voltage internally.
The A/D-translator 29 includes address translator and data translator. It includes an oscillator 290, an error checking & correction (ECC) circuit 29E, a page register/fault memory/trim-bit circuit 29P and a smart write controller 29W. The oscillator 290 provides an internal clock signal. The ECC circuit 29E detects and corrects errors while performing ECC-decoding after data are read out from the 3D-M arrays. It also performs ECC-encoding before data are written to the 3D-M arrays (referring to U.S. Pat. No. 6,591,394, “Three-Dimensional Memory Array and Method for Storing Data Bits and ECC Bits Therein” issued to Lee et al. on Jul. 8, 2003). The page register 29P serves as an intermediate storage device between the user and the 3D-M array(s), while the fault memory/trim-bit circuit 29P performs address mapping (referring to U.S. Pat. No. 8,223,525, “Page Register Outside Array and Sense Amplifier Interface”, issued to Balakrishnan et al. on Jul. 17, 2012). The smart write controller 29W collects detected errors during programming and activates the self-repair mechanism which will reprogram the data in a redundant row (referring to U.S. Pat. No. 7,219,271, “Memory Device and Method for Redundancy/Self-Repair”, issued to Kleveland et al. on May 15, 2007). The integrated 3D-M die 20 performs both address translation and data translation internally.
The VR/VW-generator 21 and A/D-translator 29 are outside-array peripheral-circuit components 18. Because they occupy a large area on the 3D-M die 20, the integrated 3D-M die 20 has a low array efficiency. The array efficiency is defined as the ratio between the total memory area (i.e., the chip area used for memory) and the total chip area. In 3D-M, the total memory area (AM) is the chip area directly underneath user-addressable bits (not counting bits a user cannot access) and can be expressed as AM=Ac*CL=(4F2)*C3D-M/N, where CL is the storage capacity per memory level, Ac is the area of a single memory cell, C3D-M is the total storage capacity of the 3D-M, F is the address-line pitch, and N is the total number of memory levels in the 3D-M. In the following paragraphs, two 3D-M dice are examined for their array efficiencies.
As a first example, a 3-D one-time-programmable memory (3D-OTP) is disclosed in Crowley et al. “512 Mb PROM with 8 Layers of Antifuse/Diode Cells” (referring to 2003 International Solid-State Circuits Conference, FIG. 16.4.5). This 3D-OTP die has a storage capacity of 512 Mb and comprises eight memory levels manufactured at 0.25 um node. The total memory area is 4*(0.25 um)2*512 Mb/8=16 mm2. With a total chip area of 48.3 mm2, the array efficiency of the 3D-OTP die is ˜33%.
As a second example, a 3-D resistive random-access memory (3D-ReRAM) is disclosed in Liu et al. “A 130.7 mm2 2-Layer 32 Gb ReRAM Memory Device in 24 nm Technology” (referring to 2013 International Solid-State Circuits Conference, FIG. 12.1.7). This 3D-ReRAM die has a storage capacity of 32 Gb and comprises two memory levels manufactured at 24 nm node. The total memory area is 4*(24 nm)2*32 Gb/2=36.8 mm2. With a total chip area of 130.7 mm2, the array efficiency of the 3D-ReRAM die is 28%.
The example in FIGS. 1A-1B is a three-dimensional horizontal memory (3D-MH), whose basic storage units are horizontal memory levels. This cost-analysis can also be applied to a three-dimensional vertical memory (3D-MV), whose basic storage units are vertical memory strings.
U.S. Pat. No. 8,638,611 issued to Sim et al. on Jan. 28, 2014 discloses a 3D-MV. It is a vertical-NAND. Besides vertical-NAND, the 3D-ROM, 3D-RAM, 3D-memristor, 3D-ReRAM or 3D-RRAM, 3D-PCM, 3D-PMC, 3D-CBRAM disclosed above can also be arranged into 3D-MV. As illustrated in FIG. 2, a 3D-MV die 20V comprises at least a 3D-MV array 16V and a peripheral circuit 18. The 3D-MV array 16V comprises a plurality of vertical memory strings 16X, 16Y. Each memory string (e.g., 16X) comprises a plurality of vertically stacked memory cells (e.g., 8a-8h). These memory cells are coupled by at least a vertical address line. Each memory cell (e.g., 8f) comprises at least a vertical transistor, with a gate 6, an information storage layer 7 and a vertical channel 9. As an integrated 3D-MV, the 3D-MV array 16V and its peripheral circuit 18 are integrated into a single die 20V.
A notable difference between 3D-MH (FIG. 1A) and 3D-MV(FIG. 2) is that the horizontal memory levels 16A, 16B in 3D-MH do not include any portion of the substrate 0, whereas the vertical memory strings 16X, 16Y in 3D-MV include a portion of the substrate 0. In other words, the 3D-MH die 20 could comprise an under-array peripheral circuit, whereas the 3D-MV die 20V cannot comprise any under-array peripheral circuit. The peripheral circuit 18 for the 3D-MV 20V is completely located outside the 3D-MV array 16V. It comprises substrate transistors 0t and substrate interconnects 0i. The substrate transistors 0t are conventional (horizontal) transistors, which are formed in a semiconductor substrate 0. The substrate interconnects 0i are the interconnects for the substrate transistor 0t. In this example, the substrate interconnects 0i includes metal layers 0M1, 0M2.
It is a prevailing belief in the field of integrated circuit that more integration is always desired. However, this belief is no longer true for any 3D-M (including both 3D-MH and 3D-MV). For 3D-MH, because the peripheral circuit 18 comprises significantly fewer BEOL layers than the 3D-MH arrays 16, integration would force the peripheral circuit 18 to use the expensive BEOL manufacturing process of the 3D-MH arrays 16 and therefore, increases the overall 3D-MH cost. Similarly, for 3D-MV, because the vertical memory strings 16X, 16Y use a complex BEOL process whereas the peripheral circuit 18 uses a relatively simple BEOL process, integrating the vertical memory strings 16X, 16Y with their peripheral circuit 18 will force the peripheral circuit 18 to use the expensive BEOL manufacturing process for the vertical memory strings 16X, 16Y. As a result, integration does not lower the overall cost, but actually increases the overall cost of the 3D-MV.